Twenty years ago, a group of top-notch researchers led by Dr. Chenming Hu and Dr. Ping K. Ko at the University of California, Berkeley, invented a physics-based, accurate, scalable, robust, and predictive Mosfet Spice model called BSIM3. This compact model was used for circuit simulation and CMOS technology development and later became the first international industry-standard compact model.
The impact of BSIM3 — along with later BSIM family models, including BSIM4, BSIMSOI, and BSIM-CMG — cannot be overstated. It has been used by the semiconductor industry over the last 20 years, along with continuous technology innovations and process scaling down to follow Moore’s Law, from 0.25µm to 20nm, and 16/14nm FinFET and beyond. Model standardization is one of the main drivers enabling the maturity and success of the foundry-fabless business model. Standard BSIM models permitted foundries to provide accurate representation of nano-scale device characteristics efficiently handled by circuit simulation tools in big chip designs with millions or even billions of transistors.
With the industry mainstream expected to stay at 28nm for a little longer, leading foundries are expanding their existing technologies to have more varieties of technology offerings. One recent example is the announcement from TSMC about its ultra-low technology platforms at 0.13µm, 90nm, 55nm, 40nm, 28nm, and 16nm, for use in IoT and wearable device applications. Also, new structures are emerging; in particular, the 3D FinFET structure for the 16/14nm node is the one that gets the most attention being rolled out to leading-edge designs, and ultra-thin FDSOI is viewed as a promising alternative to FinFET for sub-20nm solutions.
Moving to 7nm and beyond, there will more potential solutions explored by different players, including new materials such as Germanium, III-V, and carbon, along with new structures such as gate-all-around (GAA) and nanotubes.
As we move further forward, the semiconductor industry has not set a clear direction as it did with silicon-based planer CMOS, which has dominated the industry for more than 20 years with a variety of options. Such technological varieties are needed to push the technology into smaller nodes and address the complexity needs of new big data and IoT trends.
The continuous scaling down of semiconductor devices and the use of new materials, new structures, and new process techniques all push devices to smaller sizes that can operate faster with significantly low power consumption. Ultimately, chip designers may deploy more intelligent ways of developing chips, such as neuromorphic or the quantum computing direction. A recent IBM announcement signaled its investment of additional $3 billion in next five years on future computer chips at 7nm and beyond.
Irrespective of IBM’s even more recent announcement to exit the semiconductor business, as per this article:
IBM also underscored its intent to continue its semiconductor research and development. It said the sale has no impact on a previously announced $3 billion, five-year investment in semiconductor research. It said the sale will help the company improve its focus on cloud computing, big data analytics and security.
We can use the 3V (Variety, Velocity, and Volume) model of big data to illustrate a semiconductor industry trend. As discussed above, we have the technological varieties for future semiconductor chips, which gives us the first V.
For our purposes here, we can use the second V — Velocity — to explain the ultimate goal of all these technological efforts; i.e., realizing much faster performance with much smaller size and lower power consumption (note that the Velocity explanation in the big data 3V theory is different to our interpretation here in the context of the semiconductor industry).
And, obviously, we see the third V in the semiconductor industry — Volume. IC chips are now everywhere in everyone’s daily life. Driven by IoT needs and the growing big data trend, IC volume will grow ever greater, and the data amount it carries will reach an uncountable number. Such a trend can be grouped in the traditional big data category.
In additional, IC chips have other Volume characteristics. For example, the transistor count in modern SoC chips has increased dramatically to multiple billions, and it is expected to grow continuously moving forward together with technology scaling down and design complexity scaling up. These gigascale chips will create design and fabrication challenges that impact the entire industry, including foundry, fabless, and EDA tool providers.
Looking back, the past 20 years of the semiconductor industry is a history of technology scaling down, making nanoscale devices and gigascale chips possible. Moving forward, semiconductor industry trends can be predicted by the 3V model of big data — making even smaller devices to achieve performance (Velocity), enabling more varieties of technology offerings to address big data trends and IoT needs (Variety), and being able to handle gigascale designs and volume IC chip operations (Volume). The combination of nanoscale structures with multi-dimensional variation problems and gigascale chip complexities results in challenges and difficulties in fabrication, modeling, design, simulation, and verification. It will be interesting to see how these problems are addressed and overcome.
Author: Dr. Lianfeng Yang, vice president of marketing at ProPlus Design Solutions Inc.